This invention relates to semiconductor memories and particularly to multi-level cell (MLC) flash memories with error correction code.
A flash memory cell, as well as other types of memory cells, may be configurable to store more than one voltage threshold level (VT) in one cell. Depending on the number of threshold levels, more than one bit may be stored per cell. For example, a memory cell capable of storing four threshold levels is capable of storing two bits per cell.
Aggressive scaling of process technology and demand for higher density chips present increasing reliability challenges to multi-level cell memory product development. Error correction codes (ECC) are used throughout the electronics, communications, and memory industries to counter low-level reliability problems while improving performance or reducing cost per bit. A typical error correction method involves calculating parity bits for a codeword of data. For example, a 256 bit codeword may have parity bits associated with it. The parity bits are calculated based on an error correction code.
A fundamental problem with designing error correction codes into a MLC flash memory is the one-way nature of flash programming. Error correction codes work on codewords (or other data segments). Parity bits (or parity check bits) may be generated and then associated with a codeword. Each time that a codeword is rewritten, the associated parity bits will have to change.
However, the parity bit may only change from a one to a zero because rewriting a bit from zero to one in flash memory involves a block erase. In other words, error correction codes are not practical with flash memories, which may be rewritten several times, since the associated parity bits may need to change from zero to one in response to the rewriting of a codeword.
Therefore, there is a need for alternative ways to implement error correction methods in flash memories, while allowing overwriting.